1. Technical Field
The present invention relates to wired or wireless radio systems and, more particularly, to any phase locked loop that requires a fast lock time with low phase noise.
2. Related Art
The demand for high performance universal frequency synthesizers is growing with the increasing performance and integration requirements of wireless radio frequency (RF) systems, such as cellular telephony and FM radio systems. Phase locked loop (PLL) frequency synthesis is a popular indirect frequency synthesis method for high performance applications due to its agility and the ability of synthesizing frequencies over wide bandwidths with narrow channel spacing. However, PLL synthesizer design still remains a challenging aspect of RF system design, because of the stringent requirements typically imposed on frequency synthesizers. For example, frequency synthesizers are typically required to be defined with an output frequency accuracy on the order of a few parts per million (PPM). Furthermore, in most cases, the output frequency must also be capable of being varied in small precise steps, such as a few kilo-hertz (kHz), corresponding to the RF channel spacing.
In addition to accuracy and channel spacing, other aspects of PLL frequency synthesizers influence the performance of a receiver, such as phase noise. In radio receivers, if the phase noise produced by the frequency synthesizer mixes with nearby interferers that are then converted onto the desired channel, the signal-to-noise ratio of the received signal can be adversely affected. PLL frequency synthesizers typically include a precise crystal oscillator (X-TAL) providing a reference frequency, a phase frequency detector (PFD), a charge pump (CP), a lowpass loop filter (LPF), a voltage controlled oscillator (VCO), and one or more divider blocks in the feedback path that each divide the incoming signal by some integer of either fixed or on-the-fly programmable value to produce a feedback signal. The strict phase noise requirements of PLL frequency synthesizers sometimes dictate a narrow LPF bandwidth and a low kVCO, where kVCO denotes the VCO gain (i.e., the sensitivity of the VCO to changes in the control voltage).
However, such narrow loop filter bandwidth requirements and low kVCO requirements, in combination with high divide ratios in the feedback path and low reference frequencies, increase the lock time of the PLL. As used herein, the term “lock time” refers to an indication of how fast a new frequency is established when the RF receiver commands a change in the channel. The maximum lock time allowed in typical RF systems can vary from a few microseconds (us) to a few tens of milliseconds (ms.). However, for PLL's with a low kVCO and a narrow loop filter bandwidth, the actual lock time can be orders of magnitude greater than the maximum desired lock time.
Therefore, a need exists for a PLL design for use in radio transceivers that minimizes the lock time.